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compact 600 ma, 3 mhz, step - down converter with output discharge data sheet ADP2109 rev. b informati on furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2009 C 2012 analog devices, inc. all rights reserved. features peak efficiency : 95% discharge switch function f ixed frequency operation : 3 mhz typical quiescent current : 18 a maximum load current : 6 00 ma input voltage : 2.3 v to 5.5 v uses tiny multilayer inductors and capacitors current mode architecture for fast load and line transient r esponse 100% duty - cycle low dropout mode internal synchronous rectifier internal compensation internal soft start current overload protection t hermal shutdown protection s hutdown supply current : 0.2 a 5 - ball wlcsp supporte d by ad isimpower? design tool applications pdas and palmtop computers wireless handsets digital audio, port able media players digital cameras, gps navigation units general description the ADP2109 is a high efficiency, low quiescent current step - d own dc - t o - dc converter with a n internal discharge switch that allows automatic discharge of the output capacitor in an ultra - s mall 5 - ball wlcsp package . the total solution requires only three tiny external components. it uses a proprietary high speed current mode and constant frequency pulse - width modulation ( pwm ) control scheme for excellent stability , and transient response. to ensure the longest battery life in portable applications, the ADP2109 has a power save mode that reduces the switching frequency under l ight load conditions. the ADP2109 runs on input voltages of 2.3 v to 5.5 v , which allow for single lithium or lithium polymer cell, multiple a lkaline or nimh cell s , pcmcia, usb, and other standard power sources. the maximum load current of 6 00 ma is achi evable across the input voltage range. the ADP2109 is available in fixed output voltages of 1. 8 v, 1.5 v, 1. 2 v , and 1.0 v. all versions include an internal power switch and synchronous rectifier for minimal external part count and high efficiency. the ad p2109 has an internal soft start and internal compensation . during logic - controlled shutdown, the input is disconnected from the ou tput and the ADP2109 draws less than 1 a from the input source. other key features include under voltage lockout to prevent deep battery discharge and soft start to prevent input current overshoot at startup. the ADP2109 is available in a 5 - ball wlcsp . a similar converter, t he adp2108 , provide s the same features and operations as the ADP2109 without the discharge switch and is available in both wlcsp and tsot packages with additional output voltages . typical applications circuit 07964-001 1.0v to 1.8v 10 f 1h 4.7 f 2.3v to 5.5v on off ADP2109 gnd vin en sw fb figure 1.
ADP2109 data sheet rev. b | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 typical applications circuit ............................................................ 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 input and output capacitor, recommended specifications .. 3 absolute maximum ratings ............................................................ 4 therm al resistance ...................................................................... 4 esd caution .................................................................................. 4 pin configuration and function descriptions ............................. 5 typical performance characteristics ............................................. 6 theory of operation ...................................................................... 10 control scheme .......................................................................... 10 pwm mode ................................................................................. 10 power save mode ........................................................................ 10 enable/shutdown ....................................................................... 11 discharge switch ........................................................................ 1 1 short - circuit protection ............................................................ 11 undervoltage lockout ............................................................... 11 thermal protection .................................................................... 11 soft start ...................................................................................... 11 current limit .............................................................................. 11 100% duty operation ................................................................ 11 applications information .............................................................. 12 adisimpower design tool ....................................................... 12 external component selection ................................................ 12 thermal considerations ............................................................ 13 pcb layout guidelines .............................................................. 13 evaluation board ............................................................................ 14 outline dimensions ....................................................................... 15 ordering guide .......................................................................... 15 revision history 7 /12 rev. a to rev b changes to features section ............................................................. 1 added adisimpower design tool section .................................. 12 4 / 1 0 rev. 0 to rev. a changes to ordering guide .......................................................... 1 5 4 /09 revision 0: initial version
data sheet ADP2109 rev. b | page 3 of 16 specifications v in = 3.6 v, v out = 1.8 v, t j = ?40 c to +125c for minimum/maximum specifications , and t a = 25c for typical specifications, unless otherwise noted. 1 table 1 . parameters conditions min typ max unit input characteristics input voltage range 2.3 5.5 v undervo ltage lockout threshold v in rising 2.3 v v in falling 2.05 2.15 2.25 v output characteristics output voltage accuracy pwm mode ?2 +2 % v in = 2.3 v to 5.5 v, pwm mode ?2.5 +2.5 % power save mode to pwm current threshol d 85 ma pwm to power save mode curr ent threshold 80 ma input current characteristics dc operating current i load = 0 ma, device not switching 18 30 a shutdown current en = 0 v, t a = t j = ?40c to +85c 0.2 1.0 a sw characteristics sw on resistance pfet 320 m nfet 300 m current limit pfet switch peak current limit 1100 1300 1500 ma discharge sw resistance v out = 1.0 v 150 ena ble characteristics en input high threshold 1.2 v en input low threshold 0.4 v en input leakage current en = 0 v, 3.6 v ?1 0 +1 a oscillator frequency i load = 200 ma 2.5 3.0 3.5 mhz start - up time 550 s thermal characteristics th ermal shutdown threshold 150 c thermal shutdown hysteresis 20 c 1 all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc). input and output cap acitor, recommended specifications table 2 . parameter symbol conditions min typ max unit minimum input and output capacitance c min t a = ?40c to +125c 4.7 f minimum and maximum inductance l t a = ?40c to +125c 0.3 3.0 h
ADP2109 data sheet rev. b | page 4 of 16 absolute maximum rat ings table 3 . parameter rating vin, en ?0.4 v to +6 .5 v fb, sw to gnd ? 1 .0 v to (v in + 0.2 v) operating ambient temperature range ? 40c to +85c operating junction temperature range ? 40c to +125c storage temperature range ? 65c to +150c lead temperature range ?65c to +150c soldering conditions jedec j - std -020 stresses above those listed under absolute ma ximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to abs olute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings apply individually only, not in combination. unless otherwise specified, all other voltages are referenced to gnd. the ADP2109 can be damaged when the junction temperature limits are exceeded. monitoring ambient temperature does not guara ntee that the junction temperature ( t j ) is within the specif ied temperature limits. in applications with high power dissipation and poor thermal resistance, the max imum ambient tempera - ture may have to be derated. in applications with moderate power dissipation and low pcb thermal resistance, the max - imum ambient temperature can exceed the maximum limit as long as t j is within specification limits. t j of the device is dependent on the ambient temperature (t a ) of the device , the power dissipation (pd) of the device, and the junction - to - ambient thermal resistance ( ja ) of the package. maximum t j is calculated from t a and pd using the following formula: t j = t a + ( pd ja ) thermal resistance ja is specified for a device mounted on a jedec 2s2p pcb. table 4 . thermal resistance package type ja unit 5 - ball wlcsp 105 c/w esd caution
data sheet ADP2109 rev. b | page 5 of 16 pin configuration an d function descripti ons vin gnd sw en fb t op view (bal l side down) not to scale 07964-003 1 a b c 2 bal l a1 indic a t or figure 2. pin c onfiguration table 5 . pin function descriptions p in no. mnemonic description a 1 vin power source input. vin is the source of the pfet high - side switch. bypass vin to gnd with a 2.2 f or greater ca pacitor as close to the ADP2109 as possible. a 2 gnd ground. connect all the i nput and o utput c apacitors to gnd . b sw switch node output. sw is the drain of the pfet switch and nfet synchronous rectifier. c1 en enable input. dr ive en high to turn on the adp210 9 . drive en low to turn it off and reduce the input current to 0.1 a. c2 fb feedback input of the e rror a mplifier. connect fb to the output of the switching regulator.
ADP2109 data sheet rev. b | page 6 of 16 typical performance characteristics v in = 3.6 v, t a = 25c, v en = v in , unless otherwise noted . 12 14 16 18 20 22 24 2.5 3.0 3.5 4.0 4.5 5.0 5.5 07964-004 input voltage (v) quiescent current (a) ?40c +25c +85c figure 3 . quiescent suppl y current vs . input voltage 2500 2600 2700 2800 2900 3000 3100 3200 3300 3400 3500 2.3 2.8 3.3 3.8 4.3 4.8 5.3 07964-005 input voltage (v) frequency (khz) ?40c +25c +85c figure 4 . switching frequency vs . input voltage 1.795 1.800 1.805 1.810 1.815 1.820 1.825 1.830 1.835 1.840 ?45 ?25 ?5 15 35 55 75 07964-006 temperature (c) output voltage (v) i out = 10ma i out = 150ma i out = 500ma figure 5. output voltage vs . temperature 600 700 800 900 1000 1100 1200 1300 1400 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 07964-007 input voltage (v) current limit (a) figure 6 . pmos current limit vs. input voltage 2.5 3.0 3.5 4.0 4.5 5.0 5.5 ?40c 07964-008 input voltage (v) output current (a) 0.04 0.05 0.06 0.07 0.08 0.09 0.10 0.11 0.12 0.13 0.14 0.15 +85c pwm to psm psm to pwm f igure 7 . mode transition across temperature 2.5 3.0 3.5 4.0 4.5 5.0 5.5 07964-009 input voltage (v) output current (a) 0.06 0.07 0.08 0.09 0.10 0.11 0.12 0.13 0.14 0.15 pwm to psm psm to pwm figure 8 . mode transition
data sheet ADP2109 rev. b | page 7 of 16 0 0.1 0.2 0.3 0.4 0.5 0.6 07964-010 output current (a) output voltage (v) 1.775 1.785 1.795 1.805 1.815 1.825 v in = 2.7v v in = 3.6v v in = 4.5v v in = 5.5v figure 9 . load regulation , v out = 1.8 v 0 0.1 0.2 0.3 0.4 0.5 0.6 0.990 0.995 1.000 1.005 1.010 1.015 1.020 1.025 07964-011 output current (a) output voltage (v) 0.985 v in = 2.7v v in = 3.6v v in = 4.5v v in = 5.5v figure 10 . load regulation , v ou t = 1.0 v 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 07964-012 output current (a) efficiency (%) v in = 2.7v v in = 3.6v v in = 4.5v v in = 5.5v figure 11 . efficiency , v out = 1.8 v 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 07964-013 output current (a) efficiency (%) v in = 2.7v v in = 3.6v v in = 4.5v v in = 5.5v figure 12 . efficiency , v out = 1.0 v 07964-014 ch1 50mv ch4 2v ch3 1v m 40 s a ch3 3.26v 1 4 3 t 10.80% v in sw v out figure 13 . line transient , v out = 1.8 v, power save mode , i load = 2 0 ma 07964-015 20mv ch4 2v ch3 1v m 40 s a ch3 3.26v 1 4 3 10.80% v in sw v out figure 14 . line transient , v out = 1.8 v, pwm , i load =1 00 ma
ADP2109 data sheet rev. b | page 8 of 16 07964-016 ch1 50mv ch4 2v ch3 1v m 40 s a ch3 3.26v 1 4 3 t 10.80% v in sw v out figure 15 . line transient , v out = 1.0 v 07964-017 ch1 50mv ch2 200m a ? ch4 2v m 40 s a ch2 36m a 1 2 4 t 19.80% sw v out i out figure 16 . load transient , v out = 1.8 v, 300 ma to 600 ma 07964-018 ch1 50mv ch2 250m a ch4 2v m 40 s a ch2 5m a 2 1 4 t 25.4% sw v out i out figure 17 . load transient , v out = 1.8 v, 50 ma to 300 ma 07964-019 ch1 50mv ch2 50m a ? ch4 2v m 40 s a ch2 12m a 2 1 4 t 25.4% sw v out i out figure 18 . load transient , v out = 1.8 v, 5 ma to 50 ma 07964-020 ch1 1v ch4 5v ch2 250m a ch3 5v m 40 s a ch3 2v 1 3 4 2 t 10.80% sw i l v out en figure 19 . start u p , v out = 1.8 v, 400 ma 07964-021 ch1 1v ch4 5v ch2 250m a ch3 5v m 40 s a ch3 2v 1 2 4 3 t 10.80% sw i l v out en figure 20 . s tart u p , v out = 1.8 v, 5 ma
data sheet ADP2109 rev. b | page 9 of 16 07964-022 ch1 500mv ch4 5v ch2 500m a ch3 5v m 40 s a ch3 2.1v 3 1 2 4 t 19.80% sw i l v out en figure 21 . startu p , v out = 1.0 v, 600 ma 07964-030 ch1 500mv ch4 5.00v ch3 2.00v m 4.00ms a ch1 380mv 1 3 4 t 73.40% v in = 5.5v load = 0m a v out = 1.0v v out enable sw figure 22 . typical discharge curve, v out = 1.0 v, v in = 5.5 v 07964-024 ch1 50mv ch2 500m a ch4 2v m 2 s a ch4 2.64m a 1 2 4 t 20% v out i l sw figure 23 . typical power save mode wave form , 50 ma 07964-023 ch1 20mv ch2 200m a ch4 2v m 200ns a ch4 2.64v 1 2 4 t 20% v out i l sw figure 24 . typical pwm waveform , 200 ma 120 100 80 60 40 20 0 0 time (ms) relative output voltage (%) 07964-031 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 50f 20f 10f figure 25 . discharge profile with different values of output c apacitors
ADP2109 data sheet rev. b | page 10 of 16 theory of operation gnd fb vin sw en ADP2109 07964-025 soft start undervoltage lockout oscillator thermal shutdown driver and antishoot- through psm comp low current pwm comp i limit gm error amp pwm/ psm control figure 26 . functional block diagram the ADP2109 is a step - down dc - to - dc converter that uses a fixed frequency and high speed current mode architecture. the high switching frequency and tiny 5 - ball wlcsp package allow for a small step - down dc - to - dc converter solution. the adp2 109 operate s with an input voltage of 2.3 v to 5.5 v and regula te s an output voltage down to 1.0 v. control scheme the ADP2109 operates with a fixed frequency, current mode pwm control architecture at medium to high loads for high efficiency, but it shift s to a power save mode control scheme at light loads, to lower the regulation power losses. when operating in fixed frequency pwm mode, the duty cycle of the in tegrated switches is adjusted and regulate s the outpu t voltage. when operating in power save mo de at light loads, the output voltage is controlled in a hysteretic manner, with higher v out ripple. during part of this time , the conv erter is able to stop switching and enters an idle mode, which improves conversion efficiency. pwm m ode in pwm mode, the ADP2109 operates at a fixed frequency of 3 mhz , set by an internal oscillator. at the start of each oscilla tor cycle, the pfet switch is turned on, putting a positive voltage across the inductor. current in the inductor increases until the current sense si gnal crosses the peak inductor current threshold that turns off the pfet switch and turns on the nfet syn - chronous rectifier. this puts a negative voltage across the inductor, causing the inductor current to decrease. the synchronous rectifier stays on fo r the rest of the cycle. the ADP2109 regulates the output voltage by adjusting the peak inductor current threshold. power s ave mode the ADP2109 smoothly transitions to the power save mode of operation when the loa d current decreases below the power save m ode cu rrent threshold. on entry to power save mode , an offset is induced in the pwm regulation level , which makes the output voltage rise. when it has reached a level of approx - imately 1.5 % above the pwm regulation level , pwm operation is turned off. at this point, both power switches are off and the ADP2109 enters an idle mode. c out discharges until v out falls to the pwm regulation voltage, at which point the device drive s the inductor to make v out rise again to the upper threshold. this process repeats while the load current is below the power save mode current threshold. power save mode c urrent t hreshold the power save mode curr ent threshold is set to 8 0 ma. the ADP2109 employs a scheme that enables this current to remain accurately controlled, independ ent of v in and v out levels. this scheme also ensures that there is very little hysteresis between the power save mode current thresho ld for entry to and exit from the power save mode . the power save mode current threshold has been optimized for excellent e fficiency over all load currents.
data sheet ADP2109 rev. b | page 11 of 16 e nable /s hutdown the ADP2109 starts operation with soft start when the en pin is toggled from logic low to logic high. pulling the en pin low forces the device into shutdown mode, reducing the shutdown current below 1 a . d ischarge s witch the ADP2109 has an integrated resistor of typically 150 , as shown in figure 27, to discharge the output capacitor when the en pin goes low or when the device goes into under - voltage lock out or thermal shutdown . the time to discharge is typically 200 s. 07964-002 fb figure 27 . internal discharge switch on feedback short - circuit protection the ADP2109 includes frequency fold back to prevent output current runaway on a hard short. when the voltage at the feed - back pin falls below half of the target output voltage, indicating the possibility of a hard short at the output, the switc hing fre - quency is reduced to half of the internal oscillator frequency. the reduction in the switching frequency allow s more time for the inductor to discharge, preventing a runaway of output current. u ndervoltage l ockout to protect against battery discharge, undervoltage lockout circuitry is integrated on the ADP2109 . if the input voltage drops below the 2.15 v undervolta ge lockout ( uvlo ) thre - shold, the ADP2109 shut s down and both the power switch and synchronous rectifier turn off. when the voltage rises above the uvlo thre shold, the soft start period is initiated, and the part is enabled. t hermal protection i n the ev ent the ADP2109 junction temperatures rise above 150c , the thermal shutdown circuit turns off the converter. extreme junction temperatures can be the result of high current opera - tion, poo r circuit board design, and/or high ambient tempera ture. a 2 0 c hys t eresis is included so that when thermal shutdown occur s, the ADP2109 do es not r eturn to operation until the on - chip temperature drops below 13 0c. when coming out of thermal shutdown, soft start is initiated. s oft s tart the ADP2109 has an internal soft start function that ramps the output voltage in a controlled manner upon startup, there by limiting the inrush current. this prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter. a fter the en pin is driven high , internal circuits start to power up . the time require d to settle after the en pin is driven high is called t he power - up time. after the internal circuits are powe red up , the soft start ramp is initiated and the output capaci tor is charged linearly until the output voltage is in regulation. the time required for the output voltage to ramp is called the soft start time. start - up time in the ADP2109 is the measure of when the outp ut is in regulation after the en pin is driven h igh. start - up time consists of the power - up time and soft start time. current limit the ADP2109 has protection circuitry to limit the a mount of positive current flowing through the pfet switch and through the synchronous rectifier. the positive current lim it on the power switch limits the amount of current that can fl ow from the input to the output . t he negative current limit prevents the inductor current from reversing direction and flowing out of the load. 100% duty o peration with a drop in v in , or an inc rease in i load , the ADP2109 reach es the limit where, even with the pfet switch on 100% of the time, v out drop s bel ow the desired output voltage. at this limit, the ADP2109 smoothly transition s to a mode whe re the pfet switch stays on 100% of the time. wh en the input conditions change again and the required duty cycle falls, the ADP2109 immediately restart s pwm regulation without allowing overshoot on v out .
ADP2109 data sheet rev. b | page 12 of 16 applications information adisimpower design t ool the ADP2109 is supported by adisimpower design tool set. adisimpower is a collection of tools that produce complete power designs optimized for a specific design goal. the tools enable the user to gene rate a full schematic, bill of materials, and calculate performance in minutes. adisimpower can optimize designs for cost, area, efficiency, and parts count while taking into consideration the operating co nditions and limitations of the ic and all real external components. for more information about adisimpower design tools, refer to www.analog.com/adisimpowe r . the tool set is available from this website, and users can also request an unpopulated board through the tool. external component s election p arameters like efficiency an d transient response can be affected by varying the choice of external components i n the applications circuit , as shown i n figure 1 . inductor the h igh switching frequency of the ADP2109 allows for the selection of small chip inductors. for best performance, us e i nductor values between 0.7 h and 3 h. recommended ind uctors are shown in table 6 . the peak - to - peak inductor current ripple is calculated using the following equation : l f v v v v i sw in out in out ripple ? = ) ( w here : f sw is the switching frequency . l is the inductor valu e. the minimum dc current rating of the inductor must be greater than the inductor peak current . the inductor peak current i s calculated using the following equation: 2 ) ( ripple max load peak i i i + = inductor conduction losses are caused by the flow of current thro ugh the inductor, which has an associated i nternal dcr. larger sized inductors have smaller dcr, which may decrease inductor conduction losses. inductor core losses are related to the magnetic permeability of the core material. because the ADP2109 is a hig h switching frequency dc - to - dc converter, shielded ferrite core material is recommended for its low core losses and low emi. table 6 . suggested 1.0 h inductors vendor model dimensions i sat (ma) dcr (m) murata lqm2hpn1r0m 2.5 2. 0 1.1 1500 90 coilcraft lps3010 - 102 3.0 3.0 0.9 1700 85 toko mdt2520 - cn 2.5 2 .0 1.2 1800 100 tdk cpl2512t 2.5 1.5 1.2 1500 100 output capacitor higher output capacitor values reduce the output voltage ripple and improve load transient res ponse. when choosing this value , it is also important to account for the loss of capacitance due to output voltage dc bias. ceramic ca pacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied volta ge. capacitors must have a dielectric that is adequate to ensure the minimum capacitance over the necessary temper - ature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recommended for best performance. y5v and z5u dielectrics are not recom - mended for use with any dc - to - dc converter because of their poor temperature and dc bias characteristics. t he worst - case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage is calculated using the following equation : c eff = c out (1 C tempco ) 1(1 C tol ) w here : c eff is the effective capac itance at the operating voltage. tempco is the worst - case capacitor temperature coefficien t. tol is the worst - case component tolerance. in this example, the worst - case temperature coefficient ( tempco ) over ? 40c to +85c is assumed to be 15% for an x5r dielectric . the tolerance of the capacitor ( tol ) is assumed to be 10%, and c out is 9.2481 f at 1.8 v from the graph in figure 28. substituting these values in the equation yields c ef f = 9.2481 f (1 C 0.15) (1 C 0.1) = 7.0747 f to guarantee the performance of the ADP2109 , it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. 0 2 4 6 8 10 12 0 1 2 3 4 5 6 07964-026 dc bias voltage (v) capacitance (f) figure 28 . typical capacitor performance
data sheet ADP2109 rev. b | page 13 of 16 the peak - to - peak output voltage ripple for a chosen output capacitor and inductor values is calculat ed using the following equation : ( ) out sw ripple out sw in ripple c f i c l f v v = = 8 2 2 capacitors with lower equivalent series resista nce (esr) are preferred t o guarantee low output voltage ripple , as shown in the following equation : ripple ripple cout i v esr the effective capacitance needed for stability, which includes temperature and dc bias effects, i s 7 f. table 7 . suggested 10 f capacitors vendor type model case size voltage rating (v) murata x5r grm188r60j106 0603 6.3 t aiyo yuden x5r jmk107bj106 0603 6.3 tdk x5r c1608jb0j106k 0603 6.3 i nput capacitor higher value input capacitors help to reduce the input voltage ripple and improve transient response. maximum input capacitor current is calculated using the following equation : in out in out max load cin v v v v i i ) ( ) ( ? to minimize s upply noise , place the input capacitor as close as possible to the vin pin of the ADP2109 ic . a s with the output capacitor, a low esr capacitor is recommended. the list of recommended capacitors is shown in table 8 . table 8 . suggested 4.7 f capacitors vendor type model case size voltage rating (v) murata x5r grm188r60j475me1 9 0603 6.3 taiyo yuden x5r jmk107bj475 0603 6.3 tdk x5r c1608x5r0j475 0603 6.3 thermal c onsiderations because of t he high efficiency of the ADP2109 , only a small am ount of power is dissipated inside the ADP2109 package , which reduces thermal constraints. however, in applications with maximum loads at high ambient temperature, low supply voltage, and high duty cycle, the heat dissipated in the package is great enough that it may cause the junction temperature of the die to exceed the maximum junction temperature of 125c. if the junction temperature exceeds 150c, the converter goes into thermal shutdown. it recovers when the junction temperature falls below 130c. th e junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to power dissipation, as shown in the following equation : t j = t a + t r w here : t j is the junction temperature. t a is the ambient temperature . t r is the rise in temperature of the package due to power dissipation to it. the rise in temperature of the package is directly proportional to the power dissipation in the package. the proportionality constant for this relationship is the thermal resistance from the junction of the die to the ambient temperature, as shown in the following equation : t r = ja pd w here : t r is the rise of tempera ture of the package. ja is the thermal resistance from the junction of the die to the a mbient temperature of the package . pd is the power dissipation in the package. pcb layout guideline s poor layout can affect ADP2109 performance causing electromagnetic interference (emi) and electromagnetic compatibility (emc) problems , ground bounce , and voltage losses. poor layout can also affect regulation and stability. a good layout is implemented using the following rules: ? place the inductor, input capacitor , and output capacitor close to the ic using short tracks. these components carry high switch ing frequencies and the large tracks act like antennas. ? route the output voltage path away from the inductor and sw node to minimize n oise and magnetic interference. ? maximi z e the size of ground metal on the component side to help with thermal dissipation. ? use a ground plane with several vias connecting to the component side ground to further reduce noise interfe - rence on sensitive circuit nodes.
ADP2109 data sheet rev. b | page 14 of 16 evaluation board v out gnd out v out ADP2109 tb3 tb4 c out 10 f l1 1h u1 1 b c2 a1 v in c1 a2 gnd 2 c in 4.7 f 07964-027 v in en en vin sw fb en tb1 tb2 gnd in tb5 figure 29 . evaluation board schematic 07964-028 figure 30 . top layer, recommended layout 07964-029 figure 31 . bottom layer, recommended layout
data sheet ADP2109 rev. b | page 15 of 16 outline dimensions 02 1 109-b a b c 0.657 0.602 0.546 1.06 1.02 0.98 1.49 1.45 1.41 1 2 bot t om view (bal l side up) t op view (bal l side down) 0.330 0.310 0.290 0.866 ref 0.022 ref sea ting plane 0.50 ref 0.355 0.330 0.304 0.280 0.250 0.220 coplanarit y 0.04 0.50 bal l a1 identifier figure 32 . 5- ball wafer level chip scale package [wlcsp] (cb - 5 - 3) dimensions shown in millimet ers ordering guide model 1 temperature range output voltage (v) package description package option branding ADP2109acbz - 1.0-r7 C 40c to + 12 5c 1.0 5 - ball wafer level chip scale package [wlcsp] cb -5 -3 l9d ADP2109acbz - 1.2-r7 C 40c to + 12 5c 1.2 5 - ball w afer level chip scale package [wlcsp] cb -5 -3 l9e ADP2109acbz - 1.5 -r7 C 40c to + 12 5c 1.5 5 - ball wafer level chip scale package [wlcsp] cb -5 -3 lda ADP2109acbz - 1.8 - r7 C 40c to + 12 5c 1.8 5 - ball wafer level chip scale package [wlcsp] cb - 5 - 3 l9f ADP2109cb -1 .8evalz evaluation board for 1.8 v 1 z = rohs compliant part.
ADP2109 data sheet rev. b | page 16 of 16 notes ? 2009 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07964 - 0- 7/12(b)

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